AI Insight
Researchers developed a vertical field-effect transistor using two-dimensional materials with channel and contact lengths below 10 nanometers, addressing a critical challenge in semiconductor miniaturization. The device architecture stacks atomically thin layers of semiconducting and metallic 2D materials vertically rather than laterally, enabling extreme scaling while maintaining electrostatic control. The transistor demonstrated competitive performance metrics including high current density and effective gate control at these ultrashort dimensions.
Why it matters
This work provides a pathway for continued transistor scaling beyond the limitations facing conventional silicon-based devices, potentially extending Moore's Law. The vertical architecture could enable denser, more energy-efficient computer chips for future electronics, though significant engineering challenges remain before commercial implementation.